1. Field of the Invention
The present invention relates to driving a display panel by applying a sustain pulse to an electrode structure forming a display cell, such as a Plasma Display Panel (PDP).
2. Description of the Related Art
In a three-electrode surface-discharge plasma display panel (PDP), address electrode lines A1, A2, . . . , and Am, dielectric layers, Y-electrode lines Y1, . . . , and Yn, X-electrode lines X1, . . . , and Xn, a phosphor layer, partition walls, and an MgO protective layer are disposed between front and rear glass substrates of a surface-discharge PDP
The address electrode lines A1, A2, . . . , and Am are formed on a front side of the rear glass substrate in the form of a predetermined pattern. The entire surface of the lower dielectric layer is coated in the front of the address electrode lines A1, A2, . . . , and Am. The partition walls are formed on a front side of the lower dielectric layer to be parallel to the address electrode lines A1, A2, . . . , and Am. The partition walls partition off a discharge area of each display cell and prevent optical cross-talk between the display cells. The phosphor layer is formed between the partition walls.
The X-electrode lines X1, . . . , and Xn and the Y-electrode lines Y1, . . . , and Yn are formed on a rear side of the front glass substrate in the form of a predetermined pattern to be orthogonal to the address electrode lines A1, A2, . . . , and Am. A corresponding display cell is formed at cross points of the X-electrode lines X1, . . . , and Xn and the Y-electrode lines Y1, . . . , and Yn. Each of the X-electrode lines X1, . . . , and X1, and each of the Y-electrode lines Y1, . . . , and Yn are formed in such a manner that transparent electrode lines Xna and Yna formed of a transparent conductive material such as Indium Tin Oxide (ITO) and metallic electrode lines Xnb and Ynb used in improving conductivity are combined with one another. The front dielectric layer is formed in such a manner that the entire surface of the front dielectric layer is coated at rear sides of the X-electrode lines X1, . . . , and Xn and the Y-electrode lines Y1, . . . , and Yn. The protective layer for protecting the PDP from a strong electric field, for example, an MgO layer, is formed in such a manner that the entire surface of the MgO layer is coated on a rear side of the front dielectric layer. A gas used in forming the plasma is sealed in a discharge space.
In a method of driving such a PDP by which reset, addressing, and display sustain steps are sequentially performed in a unit subfield is generally supplied to the PDP. In a reset step, charge states of all display cells to be driven are uniform. In an addressing step, charge states of display cells to be selected and charge states of display cells that will not be selected are set. In a display sustain step, display discharge is performed in display cells to be selected. In this case, plasma is generated from the gas used in forming plasma of the display cells performing display discharge, the phosphor layer of the display cells is excited by radiating ultraviolet rays from the plasma to generate light.
An apparatus for driving the PDP includes an image processor, a logic controller, an address driver, an X-driver, and a Y-driver. The image processor converts an external analog image signal into a digital signal and generates internal image signals, for example, 8-bit red (R), green (G), and blue (B) image data, a clock signal, and vertical and horizontal synchronous signals. The logic controller generates driving control signals SA, SY, and SX in response to the internal image signals generated by the image processor. The address driver generates display data signals by processing the address signal SA from the driving control signals SA, SY, and SX generated by the logic controller and supplies the display data signals to address electrode lines. The X-driver processes the X-driving control signal SX from the driving control signals SA, SY, and SX generated by the logic controller and supplies the X-driving control signal SX to X-electrode lines. The Y-driver processes the Y-driving control signal SY from the driving control signals SA, SY, and SX generated by the logic controller and supplies the Y-driving control signal SX to Y-electrode lines.
An example of a widely-used address-display separation driving method is included in U.S. Pat. No. 5,541,618.
FIG. 3 is a view of a conventional address-display separation driving method to be performed on Y-electrode lines of the PDP 1 of FIG. 1. Referring to FIG. 3, a unit frame can be divided into a predetermined number of subfields, for example, eight subfields SF1, . . . , and SF8, in order to realize time division gray-scale display. In addition, each of the subfields SF1, . . . , and SF8 is divided into a reset period (not shown), address periods A1, . . . , and A8, and discharge-sustain periods S1, . . . , and 8.
In each of the address periods A1, . . . , and A8, display data signals are supplied to the address electrode lines (A1, A2, . . . , and Am of FIG. 1) and simultaneously, a corresponding scan pulse is sequentially supplied to each of Y-electrode lines Y1, Y2, . . . , and Yn.
In each of the discharge-sustain periods S1, . . . , and S8, display-discharge pulses are alternately supplied to the Y-electrode lines Y1, Y2, . . . , and Yn and X-electrode lines X1, X2, . . . , and Xn such that display discharge occurs in discharge cells in which wall charges are formed in the address periods A1, . . . , and A8.
The luminance of a PDP is proportional to the number of discharge-sustain pulses in the discharge-sustain periods S1, . . . , and S8 of the unit frame. When one frame used in forming one image is represented as eight subfields and a 256 level gray scale, different number of sustain pulses can be allocated to each subfield at the rates of 1, 2, 4, 8, 16, 32, 64, and 128. In order to realize the luminance of a 133 level gray scale, cells are addressed and discharge sustained for a first subfield period, a third subfield period, and an eighth subfield period.
The number of sustain pulses to be allocated to each subfield can vary according to weighed values of the subfields in an automatic power control (APC) step. In addition, the number of sustain pulses to be allocated to each subfield can be diversely modified in consideration of gamma characteristics or panel characteristics. For example, a gray scale allocated to a fourth subfield can be reduced from 8 to 6, and a gray scale allocated to a sixth subfield can be increased from 32 to 34. In addition, the number of subfields used in forming one frame can be diversely modified according to design specifications.
The driving signals for driving the PDP include signals supplied to an address electrode A, a common electrode X, and scan electrodes Y1, Y2, . . . , and Yn in one subfield SF using an address display separated driving method for an AC PDP. One subfield SF includes a reset period PR, an address period PA, and a discharge-sustain period PS.
In the reset period PR, reset pulses are supplied to scan lines of all groups and write discharge is forcibly performed such that states of wall charges of all cells are reset. The reset period PR is performed before the address period PA over the entire screen such that wall charges are disposed in the form of uniform and desired distribution. Wall charge conditions are similar to one another in the cells reset by the reset period PR. After the reset period PR has been performed, the address period PA is performed. In this case, in the address period PA, a bias voltage Ve is supplied to the common electrode X and the scan electrodes Y1, Y2, . . . , and Yn and the address electrodes A1, . . . , and Am are turned on at the same time in positions of cells to be displayed so that display cells are selected. After the address period PA has been performed, sustain pulses Vs are alternately supplied to the common electrode X and the scan electrodes Y1, Y2, . . . , and Yn such that the discharge-sustain period PS is performed. Voltages VG having a low level are supplied to the address electrodes A1, . . . , and Am during the discharge-sustain period PS.
The luminance of a PDP is adjusted by the number of discharge-sustain pulses. As the number of discharge-sustain pulses in one subfield or one TV field increases, the luminance of the PDP increases.
An object of a display apparatus of Korean Patent Publication No. 2002-0002250 is to solve problems due to noise occurring in a display screen caused by a large volume of electron waves or magnetic fields generated when a plurality of digital signals having the same phase are transited in an address period at the same time or the electron waves or electric fields have an effect on another device or circuit. To this end, the apparatus of the Patent Publication is characterized in that digital data having different phases are transmitted to each of a plurality of address electrode driving circuits.
However, in the above-described Patent Publication, by applying voltages to each group of address electrodes at a predetermined time difference Δt, noise is prevented from occurring due to electron waves etc. However, due to a uniform time difference, a time delay inevitably occurs in each scan operation in one line. As a result, an address period can be lengthened.